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添加 'ocs/tempete-786-1-onoc1.yaml'

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xz_ocs 1 month ago
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      ocs/tempete-786-1-onoc1.yaml

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ocs/tempete-786-1-onoc1.yaml
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type: batch1
mode_id: 21436587
mode_name: onoc1
usage: [ep8-p1]
registers_table:
- name: "CURR_STAGE2"
description: "TIA:CURR_STAGE2"
registers:
- { lane: 1, bank: 0, page: 0xCD, offset: 0xA1, rw: "rw", valid_range: [0,255], recommended: 144}
- { lane: 2, bank: 0, page: 0xCD, offset: 0xA3, rw: "rw", valid_range: [0,255], recommended: 144}
- { lane: 3, bank: 0, page: 0xCD, offset: 0xA5, rw: "rw", valid_range: [0,255], recommended: 144}
- { lane: 4, bank: 0, page: 0xCD, offset: 0xA7, rw: "rw", valid_range: [0,255], recommended: 144}
- { lane: 5, bank: 0, page: 0xCD, offset: 0xA9, rw: "rw", valid_range: [0,255], recommended: 144}
- { lane: 6, bank: 0, page: 0xCD, offset: 0xAB, rw: "rw", valid_range: [0,255], recommended: 144}
- { lane: 7, bank: 0, page: 0xCD, offset: 0xAD, rw: "rw", valid_range: [0,255], recommended: 144}
- { lane: 8, bank: 0, page: 0xCD, offset: 0xAF, rw: "rw", valid_range: [0,255], recommended: 144}
- name: "VPEAK"
description: "TIA:PEAK"
registers:
- { lane: 1, bank: 0, page: 0xB2, offset: 0xC0, size: 2, rw: "r" }
- { lane: 2, bank: 0, page: 0xB2, offset: 0xC2, size: 2, rw: "r" }
- { lane: 3, bank: 0, page: 0xB2, offset: 0xC4, size: 2, rw: "r" }
- { lane: 4, bank: 0, page: 0xB2, offset: 0xC6, size: 2, rw: "r" }
- { lane: 5, bank: 0, page: 0xB2, offset: 0xC8, size: 2, rw: "r" }
- { lane: 6, bank: 0, page: 0xB2, offset: 0xCA, size: 2, rw: "r" }
- { lane: 7, bank: 0, page: 0xB2, offset: 0xCC, size: 2, rw: "r" }
- { lane: 8, bank: 0, page: 0xB2, offset: 0xCE, size: 2, rw: "r" }
- name: "MGC"
description: "TIA:MGC"
registers:
- { lane: 1, bank: 1, page: 0xC2, offset: 0xF1, rw: "rw", value: 128, valid_range: [100, 220], step: 1 }
- { lane: 2, bank: 1, page: 0xC2, offset: 0xF3, rw: "rw", value: 128, valid_range: [100, 220], step: 1 }
- { lane: 3, bank: 1, page: 0xC2, offset: 0xF5, rw: "rw", value: 128, valid_range: [100, 220], step: 1 }
- { lane: 4, bank: 1, page: 0xC2, offset: 0xF7, rw: "rw", value: 128, valid_range: [100, 220], step: 1 }
- { lane: 5, bank: 1, page: 0xC2, offset: 0xF9, rw: "rw", value: 125, valid_range: [100, 220], step: 1 }
- { lane: 6, bank: 1, page: 0xC2, offset: 0xFB, rw: "rw", value: 125, valid_range: [100, 220], step: 1 }
- { lane: 7, bank: 1, page: 0xC2, offset: 0xFD, rw: "rw", value: 125, valid_range: [100, 220], step: 1 }
- { lane: 8, bank: 1, page: 0xC2, offset: 0xFF, rw: "rw", value: 125, valid_range: [100, 220], step: 1 }
- name: "AGC_ENABLE"
description: "TIA:AGC_EN"
registers:
- { lane: 1, bank: 0, page: 0xCC, offset: 0x87, size: 2, value: 0 } # BIT0
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