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#***XZ DRV***
register_configs:
- name: "mbias1"
description: "DRV:m bais1"
registers:
- { lane: 1, bank: 0, page: 0xC1, offset: 0x90, value: 0 } # bit0-3
- { lane: 2, bank: 0, page: 0xC1, offset: 0xB0, value: 0 } # bit0-3
- { lane: 3, bank: 0, page: 0xC1, offset: 0xD0, value: 0 } # bit0-3
- { lane: 4, bank: 0, page: 0xC1, offset: 0xF0, value: 0 } # bit0-3
- { lane: 5, bank: 0, page: 0xC2, offset: 0x90, value: 0 } # bit0-3
- { lane: 6, bank: 0, page: 0xC2, offset: 0xB0, value: 0 } # bit0-3
- { lane: 7, bank: 0, page: 0xC2, offset: 0xD0, value: 0 } # bit0-3
- { lane: 8, bank: 0, page: 0xC2, offset: 0xF0, value: 0 } # bit0-3
- name: "mbias2"
description: "DRV:m bais2"
registers:
- { lane: 1, bank: 0, page: 0xC1, offset: 0x90, value: 0 } # bit4-7
- { lane: 2, bank: 0, page: 0xC1, offset: 0xB0, value: 0 } # bit4-7
- { lane: 3, bank: 0, page: 0xC1, offset: 0xD0, value: 0 } # bit4-7
- { lane: 4, bank: 0, page: 0xC1, offset: 0xF0, value: 0 } # bit4-7
- { lane: 5, bank: 0, page: 0xC2, offset: 0x90, value: 0 } # bit4-7
- { lane: 6, bank: 0, page: 0xC2, offset: 0xB0, value: 0 } # bit4-7
- { lane: 7, bank: 0, page: 0xC2, offset: 0xD0, value: 0 } # bit4-7
- { lane: 8, bank: 0, page: 0xC2, offset: 0xF0, value: 0 } # bit4-7
- name: "mbias3"
description: "DRV:m bais3"
registers:
- { lane: 1, bank: 0, page: 0xC1, offset: 0x91, value: 0 } # bit0-3
- { lane: 2, bank: 0, page: 0xC1, offset: 0xB1, value: 0 } # bit0-3
- { lane: 3, bank: 0, page: 0xC1, offset: 0xD1, value: 0 } # bit0-3
- { lane: 4, bank: 0, page: 0xC1, offset: 0xF1, value: 0 } # bit0-3
- { lane: 5, bank: 0, page: 0xC2, offset: 0x91, value: 0 } # bit0-3
- { lane: 6, bank: 0, page: 0xC2, offset: 0xB1, value: 0 } # bit0-3
- { lane: 7, bank: 0, page: 0xC2, offset: 0xD1, value: 0 } # bit0-3
- { lane: 8, bank: 0, page: 0xC2, offset: 0xF1, value: 0 } # bit0-3
- name: "mbias4"
description: "DRV:m bais4"
registers:
- { lane: 1, bank: 0, page: 0xC1, offset: 0x91, value: 0 } # bit4-7
- { lane: 2, bank: 0, page: 0xC1, offset: 0xB1, value: 0 } # bit4-7
- { lane: 3, bank: 0, page: 0xC1, offset: 0xD1, value: 0 } # bit4-7
- { lane: 4, bank: 0, page: 0xC1, offset: 0xF1, value: 0 } # bit4-7
- { lane: 5, bank: 0, page: 0xC2, offset: 0x91, value: 0 } # bit4-7
- { lane: 6, bank: 0, page: 0xC2, offset: 0xB1, value: 0 } # bit4-7
- { lane: 7, bank: 0, page: 0xC2, offset: 0xD1, value: 0 } # bit4-7
- { lane: 8, bank: 0, page: 0xC2, offset: 0xF1, value: 0 } # bit4-7
- name: "mbias5"
description: "DRV:m bais5"
registers:
- { lane: 1, bank: 0, page: 0xC1, offset: 0x92, value: 0 } # bit0-4
- { lane: 2, bank: 0, page: 0xC1, offset: 0xB2, value: 0 } # bit0-4
- { lane: 3, bank: 0, page: 0xC1, offset: 0xD2, value: 0 } # bit0-4
- { lane: 4, bank: 0, page: 0xC1, offset: 0xF2, value: 0 } # bit0-4
- { lane: 5, bank: 0, page: 0xC2, offset: 0x92, value: 0 } # bit0-4
- { lane: 6, bank: 0, page: 0xC2, offset: 0xB2, value: 0 } # bit0-4
- { lane: 7, bank: 0, page: 0xC2, offset: 0xD2, value: 0 } # bit0-4
- { lane: 8, bank: 0, page: 0xC2, offset: 0xF2, value: 0 } # bit0-4
- name: "vctrl1"
description: "DRV:vctrl1"
registers:
- { lane: 1, bank: 0, page: 0xC1, offset: 0x86, value: 0 }
- { lane: 2, bank: 0, page: 0xC1, offset: 0xA6, value: 0 }
- { lane: 3, bank: 0, page: 0xC1, offset: 0xC6, value: 0 }
- { lane: 4, bank: 0, page: 0xC1, offset: 0xE6, value: 0 }
- { lane: 5, bank: 0, page: 0xC2, offset: 0x86, value: 0 }
- { lane: 6, bank: 0, page: 0xC2, offset: 0xA6, value: 0 }
- { lane: 7, bank: 0, page: 0xC2, offset: 0xC6, value: 0 }
- { lane: 8, bank: 0, page: 0xC2, offset: 0xE6, value: 0 }
- name: "vctrl2"
description: "DRV:vctrl2"
registers:
- { lane: 1, bank: 0, page: 0xC1, offset: 0x85, value: 0 }
- { lane: 2, bank: 0, page: 0xC1, offset: 0xA5, value: 0 }
- { lane: 3, bank: 0, page: 0xC1, offset: 0xC5, value: 0 }
- { lane: 4, bank: 0, page: 0xC1, offset: 0xE5, value: 0 }
- { lane: 5, bank: 0, page: 0xC2, offset: 0x85, value: 0 }
- { lane: 6, bank: 0, page: 0xC2, offset: 0xA5, value: 0 }
- { lane: 7, bank: 0, page: 0xC2, offset: 0xC5, value: 0 }
- { lane: 8, bank: 0, page: 0xC2, offset: 0xE5, value: 0 }
- name: "vctrl3"
description: "DRV:vctrl3"
registers:
- { lane: 1, bank: 0, page: 0xC1, offset: 0x81, value: 0 }
- { lane: 2, bank: 0, page: 0xC1, offset: 0xA1, value: 0 }
- { lane: 3, bank: 0, page: 0xC1, offset: 0xC1, value: 0 }
- { lane: 4, bank: 0, page: 0xC1, offset: 0xE1, value: 0 }
- { lane: 5, bank: 0, page: 0xC2, offset: 0x81, value: 0 }
- { lane: 6, bank: 0, page: 0xC2, offset: 0xA1, value: 0 }
- { lane: 7, bank: 0, page: 0xC2, offset: 0xC1, value: 0 }
- { lane: 8, bank: 0, page: 0xC2, offset: 0xE1, value: 0 }
- name: "v1_if"
description: "DRV:v1_if"
registers:
- { lane: 1, bank: 0, page: 0xC1, offset: 0x87, value: 0 }
- { lane: 2, bank: 0, page: 0xC1, offset: 0xA7, value: 0 }
- { lane: 3, bank: 0, page: 0xC1, offset: 0xC7, value: 0 }
- { lane: 4, bank: 0, page: 0xC1, offset: 0xE7, value: 0 }
- { lane: 5, bank: 0, page: 0xC2, offset: 0x87, value: 0 }
- { lane: 6, bank: 0, page: 0xC2, offset: 0xA7, value: 0 }
- { lane: 7, bank: 0, page: 0xC2, offset: 0xC7, value: 0 }
- { lane: 8, bank: 0, page: 0xC2, offset: 0xE7, value: 0 }
- name: "v2_if"
description: "DRV:v2_if"
registers:
- { lane: 1, bank: 0, page: 0xC1, offset: 0x84, value: 0 }
- { lane: 2, bank: 0, page: 0xC1, offset: 0xA4, value: 0 }
- { lane: 3, bank: 0, page: 0xC1, offset: 0xC4, value: 0 }
- { lane: 4, bank: 0, page: 0xC1, offset: 0xE4, value: 0 }
- { lane: 5, bank: 0, page: 0xC2, offset: 0x84, value: 0 }
- { lane: 6, bank: 0, page: 0xC2, offset: 0xA4, value: 0 }
- { lane: 7, bank: 0, page: 0xC2, offset: 0xC4, value: 0 }
- { lane: 8, bank: 0, page: 0xC2, offset: 0xE4, value: 0 }
- name: "RTERMB"
description: "DRV:rtermb"
registers:
- { lane: 1, bank: 0, page: 0xC1, offset: 0x94, value: 0 }
- { lane: 2, bank: 0, page: 0xC1, offset: 0xB4, value: 0 }
- { lane: 3, bank: 0, page: 0xC1, offset: 0xD4, value: 0 }
- { lane: 4, bank: 0, page: 0xC1, offset: 0xF4, value: 0 }
- { lane: 5, bank: 0, page: 0xC2, offset: 0x94, value: 0 }
- { lane: 6, bank: 0, page: 0xC2, offset: 0xB4, value: 0 }
- { lane: 7, bank: 0, page: 0xC2, offset: 0xD4, value: 0 }
- { lane: 8, bank: 0, page: 0xC2, offset: 0xF4, value: 0 }
- name: "MapEq"
description: "DRV:MapEq"
registers:
- { lane: 1, bank: 0, page: 0xB5, offset: 0x80, value: 0 } #Bit0-15
- { lane: 2, bank: 0, page: 0xB5, offset: 0x82, value: 0 } #Bit0-15
- { lane: 3, bank: 0, page: 0xB5, offset: 0x84, value: 0 } #Bit0-15
- { lane: 4, bank: 0, page: 0xB5, offset: 0x86, value: 0 } #Bit0-15
- { lane: 5, bank: 0, page: 0xB5, offset: 0x88, value: 0 } #Bit0-15
- { lane: 6, bank: 0, page: 0xB5, offset: 0x8A, value: 0 } #Bit0-15
- { lane: 7, bank: 0, page: 0xB5, offset: 0x8C, value: 0 } #Bit0-15
- { lane: 8, bank: 0, page: 0xB5, offset: 0x8E, value: 0 } #Bit0-15
#***I TIA***
- name: "vagc"
description: "TIA: VAGC"
registers:
- { lane: 1, bank: 0, page: 0xCD, offset: 0x81, value: 0 }
- { lane: 2, bank: 0, page: 0xCD, offset: 0x83, value: 0 }
- { lane: 3, bank: 0, page: 0xCD, offset: 0x85, value: 0 }
- { lane: 4, bank: 0, page: 0xCD, offset: 0x87, value: 0 }
- { lane: 5, bank: 0, page: 0xCD, offset: 0x89, value: 0 }
- { lane: 6, bank: 0, page: 0xCD, offset: 0x8B, value: 0 }
- { lane: 7, bank: 0, page: 0xCD, offset: 0x8D, value: 0 }
- { lane: 8, bank: 0, page: 0xCD, offset: 0x8F, value: 0 }
- name: "mgc"
description: "TIA:MGC"
registers:
- { lane: 1, bank: 0, page: 0xCD, offset: 0x91, value: 0 }
- { lane: 2, bank: 0, page: 0xCD, offset: 0x93, value: 0 }
- { lane: 3, bank: 0, page: 0xCD, offset: 0x95, value: 0 }
- { lane: 4, bank: 0, page: 0xCD, offset: 0x97, value: 0 }
- { lane: 5, bank: 0, page: 0xCD, offset: 0x99, value: 0 }
- { lane: 6, bank: 0, page: 0xCD, offset: 0x9B, value: 0 }
- { lane: 7, bank: 0, page: 0xCD, offset: 0x9D, value: 0 }
- { lane: 8, bank: 0, page: 0xCD, offset: 0x9F, value: 0 }
- name: "stg2"
description: "TIA:STG2"
registers:
- { lane: 1, bank: 0, page: 0xCD, offset: 0xA1, value: 0 }
- { lane: 2, bank: 0, page: 0xCD, offset: 0xA3, value: 0 }
- { lane: 3, bank: 0, page: 0xCD, offset: 0xA5, value: 0 }
- { lane: 4, bank: 0, page: 0xCD, offset: 0xA7, value: 0 }
- { lane: 5, bank: 0, page: 0xCD, offset: 0xA9, value: 0 }
- { lane: 6, bank: 0, page: 0xCD, offset: 0xAB, value: 0 }
- { lane: 7, bank: 0, page: 0xCD, offset: 0xAD, value: 0 }
- { lane: 8, bank: 0, page: 0xCD, offset: 0xAF, value: 0 }
- name: "opstg"
description: "TIA:OPSTA"
registers:
- { lane: 1, bank: 0, page: 0xCD, offset: 0xB1, value: 0 }
- { lane: 2, bank: 0, page: 0xCD, offset: 0xB3, value: 0 }
- { lane: 3, bank: 0, page: 0xCD, offset: 0xB5, value: 0 }
- { lane: 4, bank: 0, page: 0xCD, offset: 0xB7, value: 0 }
- { lane: 5, bank: 0, page: 0xCD, offset: 0xB9, value: 0 }
- { lane: 6, bank: 0, page: 0xCD, offset: 0xBB, value: 0 }
- { lane: 7, bank: 0, page: 0xCD, offset: 0xBD, value: 0 }
- { lane: 8, bank: 0, page: 0xCD, offset: 0xBF, value: 0 }
- name: "peak"
description: "TIA:PEAK"
registers:
- { lane: 1, bank: 0, page: 0xCD, offset: 0xC1, value: 0 }
- { lane: 2, bank: 0, page: 0xCD, offset: 0xC3, value: 0 }
- { lane: 3, bank: 0, page: 0xCD, offset: 0xC5, value: 0 }
- { lane: 4, bank: 0, page: 0xCD, offset: 0xC7, value: 0 }
- { lane: 5, bank: 0, page: 0xCD, offset: 0xC9, value: 0 }
- { lane: 6, bank: 0, page: 0xCD, offset: 0xCB, value: 0 }
- { lane: 7, bank: 0, page: 0xCD, offset: 0xCD, value: 0 }
- { lane: 8, bank: 0, page: 0xCD, offset: 0xCF, value: 0 }
- name: "agc_en"
description: "TIA:AGC_EN"
registers:
- { lane: 1, bank: 0, page: 0xCC, offset: 0x87, value: 0 } # BIT0
- { lane: 2, bank: 0, page: 0xCC, offset: 0x87, value: 0 } # BIT1
- { lane: 3, bank: 0, page: 0xCC, offset: 0x87, value: 0 } # BIT2
- { lane: 4, bank: 0, page: 0xCC, offset: 0x87, value: 0 } # BIT3
- { lane: 5, bank: 0, page: 0xCC, offset: 0x87, value: 0 } # BIT4
- { lane: 6, bank: 0, page: 0xCC, offset: 0x87, value: 0 } # BIT5
- { lane: 7, bank: 0, page: 0xCC, offset: 0x87, value: 0 } # BIT6
- { lane: 8, bank: 0, page: 0xCC, offset: 0x87, value: 0 } # BIT7
- name: "pol"
description: "TIA:POL"
registers:
- { lane: 1, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT0
- { lane: 2, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT1
- { lane: 3, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT2
- { lane: 4, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT3
- { lane: 5, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT4
- { lane: 6, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT5
- { lane: 7, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT6
- { lane: 8, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT7
- name: "RssCalL"
description: "TIA:RSSCALL"
registers:
- { lane: 1, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT0
- { lane: 2, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT1
- { lane: 3, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT2
- { lane: 4, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT3
- { lane: 5, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT4
- { lane: 6, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT5
- { lane: 7, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT6
- { lane: 8, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT7
- name: "RssCalH"
description: "TIA:RSSCALH"
registers:
- { lane: 1, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT0
- { lane: 2, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT1
- { lane: 3, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT2
- { lane: 4, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT3
- { lane: 5, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT4
- { lane: 6, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT5
- { lane: 7, bank: 0, page
: 0xCC, offset: 0x91, value: 0 } # BIT6
- { lane: 8, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT7
- name: "HPwrOp"
description: "TIA:HPwrOp"
registers:
- { lane: 1, bank: 0, page: 0xCC, offset: 0x9F, value: 0 } # BIT4-BIT7
- { lane: 2, bank: 0, page: 0xCC, offset: 0x9F, value: 0 } # BIT0-BIT3
- { lane: 3, bank: 0, page: 0xCC, offset: 0xA1, value: 0 } # BIT4-BIT7
- { lane: 4, bank: 0, page: 0xCC, offset: 0xA1, value: 0 } # BIT0-BIT3
- { lane: 5, bank: 0, page: 0xCC, offset: 0xA3, value: 0 } # BIT4-BIT7
- { lane: 6, bank: 0, page: 0xCC, offset: 0xA3, value: 0 } # BIT0-BIT3
- { lane: 7, bank: 0, page: 0xCC, offset: 0xA5, value: 0 } # BIT4-BIT7
- { lane: 8, bank: 0, page: 0xCC, offset: 0xA5, value: 0 } # BIT0-BIT3
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