/***I DRV***/ register_configs: - name: "ipcurrent" description: "DRV:IP CURRENT" registers: - { lane: 1, bank: 0, page: 0xC5, offset: 0x81, value: 0 } - { lane: 2, bank: 0, page: 0xC5, offset: 0x83, value: 0 } - { lane: 3, bank: 0, page: 0xC5, offset: 0x85, value: 0 } - { lane: 4, bank: 0, page: 0xC5, offset: 0x87, value: 0 } - { lane: 5, bank: 0, page: 0xC5, offset: 0x89, value: 0 } - { lane: 6, bank: 0, page: 0xC5, offset: 0x8B, value: 0 } - { lane: 7, bank: 0, page: 0xC5, offset: 0x8D, value: 0 } - { lane: 8, bank: 0, page: 0xC5, offset: 0x8F, value: 0 } - name: "opcurrent" description: "DRV:OP CURRENT" registers: - { lane: 1, bank: 0, page: 0xC5, offset: 0x91, value: 0 } - { lane: 2, bank: 0, page: 0xC5, offset: 0x93, value: 0 } - { lane: 3, bank: 0, page: 0xC5, offset: 0x95, value: 0 } - { lane: 4, bank: 0, page: 0xC5, offset: 0x97, value: 0 } - { lane: 5, bank: 0, page: 0xC5, offset: 0x99, value: 0 } - { lane: 6, bank: 0, page: 0xC5, offset: 0x9B, value: 0 } - { lane: 7, bank: 0, page: 0xC5, offset: 0x9D, value: 0 } - { lane: 8, bank: 0, page: 0xC5, offset: 0x9F, value: 0 } - name: "low freq" description: "DRV:LFREQ" registers: - { lane: 1, bank: 0, page: 0xC5, offset: 0xA1, value: 0 } - { lane: 2, bank: 0, page: 0xC5, offset: 0xA3, value: 0 } - { lane: 3, bank: 0, page: 0xC5, offset: 0xA5, value: 0 } - { lane: 4, bank: 0, page: 0xC5, offset: 0xA7, value: 0 } - { lane: 5, bank: 0, page: 0xC5, offset: 0xA9, value: 0 } - { lane: 6, bank: 0, page: 0xC5, offset: 0xAB, value: 0 } - { lane: 7, bank: 0, page: 0xC5, offset: 0xAD, value: 0 } - { lane: 8, bank: 0, page: 0xC5, offset: 0xAF, value: 0 } - name: "high freq" description: "DRV:HFREQ" registers: - { lane: 1, bank: 0, page: 0xC5, offset: 0xB1, value: 0 } - { lane: 2, bank: 0, page: 0xC5, offset: 0xB3, value: 0 } - { lane: 3, bank: 0, page: 0xC5, offset: 0xB5, value: 0 } - { lane: 4, bank: 0, page: 0xC5, offset: 0xB7, value: 0 } - { lane: 5, bank: 0, page: 0xC5, offset: 0xB9, value: 0 } - { lane: 6, bank: 0, page: 0xC5, offset: 0xBB, value: 0 } - { lane: 7, bank: 0, page: 0xC5, offset: 0xBD, value: 0 } - { lane: 8, bank: 0, page: 0xC5, offset: 0xBF, value: 0 } - name: "vgc enable" description: "DRV:VgcEn" registers: - { lane: 1, bank: 0, page: 0xC4, offset: 0xAF, value: 0 } # Bit0 - { lane: 2, bank: 0, page: 0xC4, offset: 0xAF, value: 0 } # Bit1 - { lane: 3, bank: 0, page: 0xC4, offset: 0xAF, value: 0 } # Bit2 - { lane: 4, bank: 0, page: 0xC4, offset: 0xAF, value: 0 } # Bit3 - { lane: 5, bank: 0, page: 0xC4, offset: 0xAF, value: 0 } # Bit4 - { lane: 6, bank: 0, page: 0xC4, offset: 0xAF, value: 0 } # Bit5 - { lane: 7, bank: 0, page: 0xC4, offset: 0xAF, value: 0 } # Bit6 - { lane: 8, bank: 0, page: 0xC4, offset: 0xAF, value: 0 } # Bit7 - name: "vagc set" description: "DRV:VagcSet" registers: - { lane: 1, bank: 0, page: 0xC5, offset: 0xD1, value: 0 } - { lane: 2, bank: 0, page: 0xC5 offset: 0xD3, value: 0 } - { lane: 3, bank: 0, page: 0xC5, offset: 0xD5, value: 0 } - { lane: 4, bank: 0, page: 0xC5, offset: 0xD7, value: 0 } - { lane: 5, bank: 0, page: 0xC5, offset: 0xD9, value: 0 } - { lane: 6, bank: 0, page: 0xC5, offset: 0xDB, value: 0 } - { lane: 7, bank: 0, page: 0xC5, offset: 0xDD, value: 0 } - { lane: 8, bank: 0, page: 0xC5, offset: 0xDF, value: 0 } - name: "vgc set" description: "DRV:VgcSet" registers: - { lane: 1, bank: 0, page: 0xC5, offset: 0xE1, value: 0 } - { lane: 2, bank: 0, page: 0xC5 offset: 0xE3, value: 0 } - { lane: 3, bank: 0, page: 0xC5, offset: 0xE5, value: 0 } - { lane: 4, bank: 0, page: 0xC5, offset: 0xE7, value: 0 } - { lane: 5, bank: 0, page: 0xC5, offset: 0xE9, value: 0 } - { lane: 6, bank: 0, page: 0xC5, offset: 0xEB, value: 0 } - { lane: 7, bank: 0, page: 0xC5, offset: 0xED, value: 0 } - { lane: 8, bank: 0, page: 0xC5, offset: 0xEF, value: 0 } - name: "vcom" description: "DRV:VCOM" registers: - { lane: 1, bank: 0, page: 0xC4, offset: 0x9E, value: 0 } - { lane: 2, bank: 0, page: 0xC4 offset: 0xA0, value: 0 } - { lane: 3, bank: 0, page: 0xC4, offset: 0xA2, value: 0 } - { lane: 4, bank: 0, page: 0xC4, offset: 0xA4, value: 0 } - { lane: 5, bank: 0, page: 0xC4, offset: 0xA6, value: 0 } - { lane: 6, bank: 0, page: 0xC4, offset: 0xA8, value: 0 } - { lane: 7, bank: 0, page: 0xC4, offset: 0xAA, value: 0 } - { lane: 8, bank: 0, page: 0xC4, offset: 0xAC, value: 0 } - name: "in mpd" description: "DRV:INMPD" registers: - { lane: 1, bank: 0, page: 0xC4, offset: 0xC1, value: 0 } # inmpd1 bit0-3 - { lane: 1, bank: 0, page: 0xC4, offset: 0xC1, value: 0 } # inmpd2 bit4-7 - { lane: 2, bank: 0, page: 0xC4 offset: 0xC3, value: 0 } # inmpd3 bit0-3 - { lane: 2, bank: 0, page: 0xC4 offset: 0xC3, value: 0 } # inmpd4 bit4-7 - { lane: 3, bank: 0, page: 0xC4, offset: 0xC5, value: 0 } # inmpd5 bit0-3 - { lane: 3, bank: 0, page: 0xC4, offset: 0xC5, value: 0 } # inmpd6 bit4-7 - { lane: 4, bank: 0, page: 0xC4, offset: 0xC7, value: 0 } # inmpd7 bit0-3 - { lane: 4, bank: 0, page: 0xC4, offset: 0xC7, value: 0 } # inmpd8 bit4-7 - { lane: 5, bank: 0, page: 0xC4, offset: 0xC9, value: 0 } # inmpd9 bit0-3 - { lane: 5, bank: 0, page: 0xC4, offset: 0xC9, value: 0 } # inmpd10 bit4-7 - { lane: 6, bank: 0, page: 0xC4, offset: 0xCB, value: 0 } # inmpd11 bit0-3 - { lane: 6, bank: 0, page: 0xC4, offset: 0xCB, value: 0 } # inmpd12 bit4-7 - { lane: 7, bank: 0, page: 0xC4, offset: 0xAA, value: 0 } # inmpd13 bit0-3 - { lane: 7, bank: 0, page: 0xC4, offset: 0xAA, value: 0 } # inmpd14 bit4-7 - { lane: 8, bank: 0, page: 0xC4, offset: 0xAC, value: 0 } # inmpd15 bit0-3 - { lane: 8, bank: 0, page: 0xC4, offset: 0xAC, value: 0 } # inmpd16 bit4-7 /***I TIA***/ - name: "vagc" description: "TIA: VAGC" registers: - { lane: 1, bank: 0, page: 0xCD, offset: 0x81, value: 0 } - { lane: 2, bank: 0, page: 0xCD, offset: 0x83, value: 0 } - { lane: 3, bank: 0, page: 0xCD, offset: 0x85, value: 0 } - { lane: 4, bank: 0, page: 0xCD, offset: 0x87, value: 0 } - { lane: 5, bank: 0, page: 0xCD, offset: 0x89, value: 0 } - { lane: 6, bank: 0, page: 0xCD, offset: 0x8B, value: 0 } - { lane: 7, bank: 0, page: 0xCD, offset: 0x8D, value: 0 } - { lane: 8, bank: 0, page: 0xCD, offset: 0x8F, value: 0 } - name: "mgc" description: "TIA:MGC" registers: - { lane: 1, bank: 0, page: 0xCD, offset: 0x91, value: 0 } - { lane: 2, bank: 0, page: 0xCD, offset: 0x93, value: 0 } - { lane: 3, bank: 0, page: 0xCD, offset: 0x95, value: 0 } - { lane: 4, bank: 0, page: 0xCD, offset: 0x97, value: 0 } - { lane: 5, bank: 0, page: 0xCD, offset: 0x99, value: 0 } - { lane: 6, bank: 0, page: 0xCD, offset: 0x9B, value: 0 } - { lane: 7, bank: 0, page: 0xCD, offset: 0x9D, value: 0 } - { lane: 8, bank: 0, page: 0xCD, offset: 0x9F, value: 0 } - name: "stg2" description: "TIA:STG2" registers: - { lane: 1, bank: 0, page: 0xCD, offset: 0xA1, value: 0 } - { lane: 2, bank: 0, page: 0xCD, offset: 0xA3, value: 0 } - { lane: 3, bank: 0, page: 0xCD, offset: 0xA5, value: 0 } - { lane: 4, bank: 0, page: 0xCD, offset: 0xA7, value: 0 } - { lane: 5, bank: 0, page: 0xCD, offset: 0xA9, value: 0 } - { lane: 6, bank: 0, page: 0xCD, offset: 0xAB, value: 0 } - { lane: 7, bank: 0, page: 0xCD, offset: 0xAD, value: 0 } - { lane: 8, bank: 0, page: 0xCD, offset: 0xAF, value: 0 } - name: "opstg" description: "TIA:OPSTA" registers: - { lane: 1, bank: 0, page: 0xCD, offset: 0xB1, value: 0 } - { lane: 2, bank: 0, page: 0xCD, offset: 0xB3, value: 0 } - { lane: 3, bank: 0, page: 0xCD, offset: 0xB5, value: 0 } - { lane: 4, bank: 0, page: 0xCD, offset: 0xB7, value: 0 } - { lane: 5, bank: 0, page: 0xCD, offset: 0xB9, value: 0 } - { lane: 6, bank: 0, page: 0xCD, offset: 0xBB, value: 0 } - { lane: 7, bank: 0, page: 0xCD, offset: 0xBD, value: 0 } - { lane: 8, bank: 0, page: 0xCD, offset: 0xBF, value: 0 } - name: "peak" description: "TIA:PEAK" registers: - { lane: 1, bank: 0, page: 0xCD, offset: 0xC1, value: 0 } - { lane: 2, bank: 0, page: 0xCD, offset: 0xC3, value: 0 } - { lane: 3, bank: 0, page: 0xCD, offset: 0xC5, value: 0 } - { lane: 4, bank: 0, page: 0xCD, offset: 0xC7, value: 0 } - { lane: 5, bank: 0, page: 0xCD, offset: 0xC9, value: 0 } - { lane: 6, bank: 0, page: 0xCD, offset: 0xCB, value: 0 } - { lane: 7, bank: 0, page: 0xCD, offset: 0xCD, value: 0 } - { lane: 8, bank: 0, page: 0xCD, offset: 0xCF, value: 0 } - name: "agc_en" description: "TIA:AGC_EN" registers: - { lane: 1, bank: 0, page: 0xCC, offset: 0x87, value: 0 } # BIT0 - { lane: 2, bank: 0, page: 0xCC, offset: 0x87, value: 0 } # BIT1 - { lane: 3, bank: 0, page: 0xCC, offset: 0x87, value: 0 } # BIT2 - { lane: 4, bank: 0, page: 0xCC, offset: 0x87, value: 0 } # BIT3 - { lane: 5, bank: 0, page: 0xCC, offset: 0x87, value: 0 } # BIT4 - { lane: 6, bank: 0, page: 0xCC, offset: 0x87, value: 0 } # BIT5 - { lane: 7, bank: 0, page: 0xCC, offset: 0x87, value: 0 } # BIT6 - { lane: 8, bank: 0, page: 0xCC, offset: 0x87, value: 0 } # BIT7 - name: "pol" description: "TIA:POL" registers: - { lane: 1, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT0 - { lane: 2, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT1 - { lane: 3, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT2 - { lane: 4, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT3 - { lane: 5, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT4 - { lane: 6, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT5 - { lane: 7, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT6 - { lane: 8, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT7 - name: "RssCalL" description: "TIA:RSSCALL" registers: - { lane: 1, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT0 - { lane: 2, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT1 - { lane: 3, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT2 - { lane: 4, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT3 - { lane: 5, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT4 - { lane: 6, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT5 - { lane: 7, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT6 - { lane: 8, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT7 - name: "RssCalH" description: "TIA:RSSCALH" registers: - { lane: 1, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT0 - { lane: 2, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT1 - { lane: 3, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT2 - { lane: 4, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT3 - { lane: 5, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT4 - { lane: 6, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT5 - { lane: 7, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT6 - { lane: 8, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT7 - name: "HPwrOp" description: "TIA:HPwrOp" registers: - { lane: 1, bank: 0, page: 0xCC, offset: 0x9F, value: 0 } # BIT4-BIT7 - { lane: 2, bank: 0, page: 0xCC, offset: 0x9F, value: 0 } # BIT0-BIT3 - { lane: 3, bank: 0, page: 0xCC, offset: 0xA1, value: 0 } # BIT4-BIT7 - { lane: 4, bank: 0, page: 0xCC, offset: 0xA1, value: 0 } # BIT0-BIT3 - { lane: 5, bank: 0, page: 0xCC, offset: 0xA3, value: 0 } # BIT4-BIT7 - { lane: 6, bank: 0, page: 0xCC, offset: 0xA3, value: 0 } # BIT0-BIT3 - { lane: 7, bank: 0, page: 0xCC, offset: 0xA5, value: 0 } # BIT4-BIT7 - { lane: 8, bank: 0, page: 0xCC, offset: 0xA5, value: 0 } # BIT0-BIT3