You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
275 lines
16 KiB
275 lines
16 KiB
type: batch1 |
|
mode_id: 43218765 |
|
mode_name: onoc2 |
|
usage: [ep8-p4] |
|
registers_table: |
|
- name: "tia_stage2" |
|
description: "TIA:tia_stage2" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xCD, offset: 0xA1, rw: "rw", valid_range: [0,255], recommended: 144} |
|
- { lane: 2, bank: 0, page: 0xCD, offset: 0xA3, rw: "rw", valid_range: [0,255], recommended: 144} |
|
- { lane: 3, bank: 0, page: 0xCD, offset: 0xA5, rw: "rw", valid_range: [0,255], recommended: 144} |
|
- { lane: 4, bank: 0, page: 0xCD, offset: 0xA7, rw: "rw", valid_range: [0,255], recommended: 144} |
|
- { lane: 5, bank: 0, page: 0xCD, offset: 0xA9, rw: "rw", valid_range: [0,255], recommended: 144} |
|
- { lane: 6, bank: 0, page: 0xCD, offset: 0xAB, rw: "rw", valid_range: [0,255], recommended: 144} |
|
- { lane: 7, bank: 0, page: 0xCD, offset: 0xAD, rw: "rw", valid_range: [0,255], recommended: 144} |
|
- { lane: 8, bank: 0, page: 0xCD, offset: 0xAF, rw: "rw", valid_range: [0,255], recommended: 144} |
|
|
|
- name: "vpeak" |
|
description: "TIA:vpeak" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xB2, offset: 0xC0, size: 2, rw: "r" } |
|
- { lane: 2, bank: 0, page: 0xB2, offset: 0xC2, size: 2, rw: "r" } |
|
- { lane: 3, bank: 0, page: 0xB2, offset: 0xC4, size: 2, rw: "r" } |
|
- { lane: 4, bank: 0, page: 0xB2, offset: 0xC6, size: 2, rw: "r" } |
|
- { lane: 5, bank: 0, page: 0xB2, offset: 0xC8, size: 2, rw: "r" } |
|
- { lane: 6, bank: 0, page: 0xB2, offset: 0xCA, size: 2, rw: "r" } |
|
- { lane: 7, bank: 0, page: 0xB2, offset: 0xCC, size: 2, rw: "r" } |
|
- { lane: 8, bank: 0, page: 0xB2, offset: 0xCE, size: 2, rw: "r" } |
|
|
|
- name: "mgc" |
|
description: "TIA:mgc" |
|
registers: |
|
- { lane: 1, bank: 1, page: 0xC2, offset: 0xA1, rw: "rw", value: 128, valid_range: [100, 220], step: 1 } |
|
- { lane: 2, bank: 1, page: 0xC2, offset: 0xA3, rw: "rw", value: 128, valid_range: [100, 220], step: 1 } |
|
- { lane: 3, bank: 1, page: 0xC2, offset: 0xA5, rw: "rw", value: 128, valid_range: [100, 220], step: 1 } |
|
- { lane: 4, bank: 1, page: 0xC2, offset: 0xA7, rw: "rw", value: 128, valid_range: [100, 220], step: 1 } |
|
- { lane: 5, bank: 1, page: 0xC2, offset: 0xA9, rw: "rw", value: 125, valid_range: [100, 220], step: 1 } |
|
- { lane: 6, bank: 1, page: 0xC2, offset: 0xAB, rw: "rw", value: 125, valid_range: [100, 220], step: 1 } |
|
- { lane: 7, bank: 1, page: 0xC2, offset: 0xAD, rw: "rw", value: 125, valid_range: [100, 220], step: 1 } |
|
- { lane: 8, bank: 1, page: 0xC2, offset: 0xAF, rw: "rw", value: 125, valid_range: [100, 220], step: 1 } |
|
|
|
- name: "tia_agc_en" |
|
description: "TIA:AGC_EN" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xCC, offset: 0x87, size: 2, value: 0 } # BIT0 |
|
|
|
- name: "ibias" |
|
description: "DRV:iBIAS" |
|
registers: |
|
- { lane: 1, bank: 1, page: 0xC0, offset: 0x98, size: 2, rw: "rw", value: 2150, valid_range: [2047, 3071], step: 1 } # TX1/2 |
|
- { lane: 2, bank: 1, page: 0xC0, offset: 0x9A, size: 2, rw: "rw", value: 2150, valid_range: [2047, 3071], step: 1 } # TX3/4 |
|
- { lane: 3, bank: 1, page: 0xC0, offset: 0x9C, size: 2, rw: "rw", value: 2150, valid_range: [2047, 3071], step: 1 } # TX5/6 |
|
- { lane: 4, bank: 1, page: 0xC0, offset: 0x9E, size: 2, rw: "rw", value: 2150, valid_range: [2047, 3071], step: 1 } # TX7/8 |
|
|
|
- name: "voa" |
|
description: "DRV:VOA" |
|
registers: |
|
- { lane: 1, bank: 1, page: 0xC1, offset: 0xA0, size: 2, rw: "rw", value: 128, valid_range: [0, 511], step: 1 } |
|
- { lane: 2, bank: 1, page: 0xC1, offset: 0xA2, size: 2, rw: "rw", value: 128, valid_range: [0, 511], step: 1 } |
|
- { lane: 3, bank: 1, page: 0xC1, offset: 0xA4, size: 2, rw: "rw", value: 128, valid_range: [0, 511], step: 1 } |
|
- { lane: 4, bank: 1, page: 0xC1, offset: 0xA6, size: 2, rw: "rw", value: 128, valid_range: [0, 511], step: 1 } |
|
- { lane: 5, bank: 1, page: 0xC1, offset: 0xA8, size: 2, rw: "rw", value: 125, valid_range: [0, 511], step: 1 } |
|
- { lane: 6, bank: 1, page: 0xC1, offset: 0xAA, size: 2, rw: "rw", value: 125, valid_range: [0, 511], step: 1 } |
|
- { lane: 7, bank: 1, page: 0xC1, offset: 0xAC, size: 2, rw: "rw", value: 125, valid_range: [0, 511], step: 1 } |
|
- { lane: 8, bank: 1, page: 0xC1, offset: 0xAE, size: 2, rw: "rw", value: 125, valid_range: [0, 511], step: 1 } |
|
|
|
### Common Config |
|
- name: "auto_mute" |
|
description: "DRV: Mute" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xC4, offset: 0x9F, value: 0x0 } |
|
|
|
- name: "ipcurrent" |
|
description: "DRV:IP CURRENT" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xC5, offset: 0x81, value: 100 } #117 |
|
- { lane: 2, bank: 0, page: 0xC5, offset: 0x83, value: 100 } |
|
- { lane: 3, bank: 0, page: 0xC5, offset: 0x85, value: 100 } |
|
- { lane: 4, bank: 0, page: 0xC5, offset: 0x87, value: 100 } |
|
- { lane: 5, bank: 0, page: 0xC5, offset: 0x89, value: 100 } |
|
- { lane: 6, bank: 0, page: 0xC5, offset: 0x8B, value: 100 } |
|
- { lane: 7, bank: 0, page: 0xC5, offset: 0x8D, value: 100 } |
|
- { lane: 8, bank: 0, page: 0xC5, offset: 0x8F, value: 100 } |
|
|
|
- name: "opcurrent" |
|
description: "DRV:OP CURRENT" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xC5, offset: 0x91, value: 110 } #127 |
|
- { lane: 2, bank: 0, page: 0xC5, offset: 0x93, value: 110 } |
|
- { lane: 3, bank: 0, page: 0xC5, offset: 0x95, value: 110 } |
|
- { lane: 4, bank: 0, page: 0xC5, offset: 0x97, value: 110 } |
|
- { lane: 5, bank: 0, page: 0xC5, offset: 0x99, value: 110 } |
|
- { lane: 6, bank: 0, page: 0xC5, offset: 0x9B, value: 110 } |
|
- { lane: 7, bank: 0, page: 0xC5, offset: 0x9D, value: 110 } |
|
- { lane: 8, bank: 0, page: 0xC5, offset: 0x9F, value: 110 } |
|
|
|
- name: "lowfreq_eq" |
|
description: "DRV:LFREQ" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xC5, offset: 0xA1, value: 255 } #255 |
|
- { lane: 2, bank: 0, page: 0xC5, offset: 0xA3, value: 255 } |
|
- { lane: 3, bank: 0, page: 0xC5, offset: 0xA5, value: 255 } |
|
- { lane: 4, bank: 0, page: 0xC5, offset: 0xA7, value: 255 } |
|
- { lane: 5, bank: 0, page: 0xC5, offset: 0xA9, value: 255 } |
|
- { lane: 6, bank: 0, page: 0xC5, offset: 0xAB, value: 255 } |
|
- { lane: 7, bank: 0, page: 0xC5, offset: 0xAD, value: 255 } |
|
- { lane: 8, bank: 0, page: 0xC5, offset: 0xAF, value: 255 } |
|
|
|
- name: "highfreq_eq" |
|
description: "DRV:HFREQ" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xC5, offset: 0xB1, value: 0 } |
|
- { lane: 2, bank: 0, page: 0xC5, offset: 0xB3, value: 0 } |
|
- { lane: 3, bank: 0, page: 0xC5, offset: 0xB5, value: 0 } |
|
- { lane: 4, bank: 0, page: 0xC5, offset: 0xB7, value: 0 } |
|
- { lane: 5, bank: 0, page: 0xC5, offset: 0xB9, value: 0 } |
|
- { lane: 6, bank: 0, page: 0xC5, offset: 0xBB, value: 0 } |
|
- { lane: 7, bank: 0, page: 0xC5, offset: 0xBD, value: 0 } |
|
- { lane: 8, bank: 0, page: 0xC5, offset: 0xBF, value: 0 } |
|
|
|
- name: "vagc_en" |
|
description: "DRV:Vagc Enable" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xC4, offset: 0xAF, value: 0 } # Bit0 |
|
- { lane: 2, bank: 0, page: 0xC4, offset: 0xAF, value: 0 } # Bit1 |
|
- { lane: 3, bank: 0, page: 0xC4, offset: 0xAF, value: 0 } # Bit2 |
|
- { lane: 4, bank: 0, page: 0xC4, offset: 0xAF, value: 0 } # Bit3 |
|
- { lane: 5, bank: 0, page: 0xC4, offset: 0xAF, value: 0 } # Bit4 |
|
- { lane: 6, bank: 0, page: 0xC4, offset: 0xAF, value: 0 } # Bit5 |
|
- { lane: 7, bank: 0, page: 0xC4, offset: 0xAF, value: 0 } # Bit6 |
|
- { lane: 8, bank: 0, page: 0xC4, offset: 0xAF, value: 0 } # Bit7 |
|
|
|
- name: "vagc_set" |
|
description: "DRV:VagcSet" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xC5, offset: 0xD1, value: 0 } |
|
- { lane: 2, bank: 0, page: 0xC5, offset: 0xD3, value: 0 } |
|
- { lane: 3, bank: 0, page: 0xC5, offset: 0xD5, value: 0 } |
|
- { lane: 4, bank: 0, page: 0xC5, offset: 0xD7, value: 0 } |
|
- { lane: 5, bank: 0, page: 0xC5, offset: 0xD9, value: 0 } |
|
- { lane: 6, bank: 0, page: 0xC5, offset: 0xDB, value: 0 } |
|
- { lane: 7, bank: 0, page: 0xC5, offset: 0xDD, value: 0 } |
|
- { lane: 8, bank: 0, page: 0xC5, offset: 0xDF, value: 0 } |
|
|
|
- name: "vgc_set" |
|
description: "DRV:VgcSet" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xC5, offset: 0xE1, value: 255 } |
|
- { lane: 2, bank: 0, page: 0xC5, offset: 0xE3, value: 255 } |
|
- { lane: 3, bank: 0, page: 0xC5, offset: 0xE5, value: 255 } |
|
- { lane: 4, bank: 0, page: 0xC5, offset: 0xE7, value: 255 } |
|
- { lane: 5, bank: 0, page: 0xC5, offset: 0xE9, value: 255 } |
|
- { lane: 6, bank: 0, page: 0xC5, offset: 0xEB, value: 255 } |
|
- { lane: 7, bank: 0, page: 0xC5, offset: 0xED, value: 255 } |
|
- { lane: 8, bank: 0, page: 0xC5, offset: 0xEF, value: 255 } |
|
|
|
- name: "vcom" |
|
description: "DRV:VCOM" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xC4, offset: 0x9E, value: 0 } |
|
- { lane: 2, bank: 0, page: 0xC4, offset: 0xA0, value: 0 } |
|
- { lane: 3, bank: 0, page: 0xC4, offset: 0xA2, value: 0 } |
|
- { lane: 4, bank: 0, page: 0xC4, offset: 0xA4, value: 0 } |
|
- { lane: 5, bank: 0, page: 0xC4, offset: 0xA6, value: 0 } |
|
- { lane: 6, bank: 0, page: 0xC4, offset: 0xA8, value: 0 } |
|
- { lane: 7, bank: 0, page: 0xC4, offset: 0xAA, value: 0 } |
|
- { lane: 8, bank: 0, page: 0xC4, offset: 0xAC, value: 0 } |
|
|
|
- name: "inmpd" |
|
description: "DRV:INMPD" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xC4, offset: 0xC1, value: 0 } # inmpd1 bit0-3 |
|
- { lane: 1, bank: 0, page: 0xC4, offset: 0xC1, value: 0 } # inmpd2 bit4-7 |
|
- { lane: 2, bank: 0, page: 0xC4, offset: 0xC3, value: 0 } # inmpd3 bit0-3 |
|
- { lane: 2, bank: 0, page: 0xC4, offset: 0xC3, value: 0 } # inmpd4 bit4-7 |
|
- { lane: 3, bank: 0, page: 0xC4, offset: 0xC5, value: 0 } # inmpd5 bit0-3 |
|
- { lane: 3, bank: 0, page: 0xC4, offset: 0xC5, value: 0 } # inmpd6 bit4-7 |
|
- { lane: 4, bank: 0, page: 0xC4, offset: 0xC7, value: 0 } # inmpd7 bit0-3 |
|
- { lane: 4, bank: 0, page: 0xC4, offset: 0xC7, value: 0 } # inmpd8 bit4-7 |
|
- { lane: 5, bank: 0, page: 0xC4, offset: 0xC9, value: 0 } # inmpd9 bit0-3 |
|
- { lane: 5, bank: 0, page: 0xC4, offset: 0xC9, value: 0 } # inmpd10 bit4-7 |
|
- { lane: 6, bank: 0, page: 0xC4, offset: 0xCB, value: 0 } # inmpd11 bit0-3 |
|
- { lane: 6, bank: 0, page: 0xC4, offset: 0xCB, value: 0 } # inmpd12 bit4-7 |
|
- { lane: 7, bank: 0, page: 0xC4, offset: 0xAA, value: 0 } # inmpd13 bit0-3 |
|
- { lane: 7, bank: 0, page: 0xC4, offset: 0xAA, value: 0 } # inmpd14 bit4-7 |
|
- { lane: 8, bank: 0, page: 0xC4, offset: 0xAC, value: 0 } # inmpd15 bit0-3 |
|
- { lane: 8, bank: 0, page: 0xC4, offset: 0xAC, value: 0 } # inmpd16 bit4-7 |
|
|
|
- name: "tia_vagc" |
|
description: "TIA: VAGC" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xCD, offset: 0x81, value: 0 } |
|
- { lane: 2, bank: 0, page: 0xCD, offset: 0x83, value: 0 } |
|
- { lane: 3, bank: 0, page: 0xCD, offset: 0x85, value: 0 } |
|
- { lane: 4, bank: 0, page: 0xCD, offset: 0x87, value: 0 } |
|
- { lane: 5, bank: 0, page: 0xCD, offset: 0x89, value: 0 } |
|
- { lane: 6, bank: 0, page: 0xCD, offset: 0x8B, value: 0 } |
|
- { lane: 7, bank: 0, page: 0xCD, offset: 0x8D, value: 0 } |
|
- { lane: 8, bank: 0, page: 0xCD, offset: 0x8F, value: 0 } |
|
|
|
- name: "opstg" |
|
description: "TIA:OPSTA" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xCD, offset: 0xB1, value: 0 } |
|
- { lane: 2, bank: 0, page: 0xCD, offset: 0xB3, value: 0 } |
|
- { lane: 3, bank: 0, page: 0xCD, offset: 0xB5, value: 0 } |
|
- { lane: 4, bank: 0, page: 0xCD, offset: 0xB7, value: 0 } |
|
- { lane: 5, bank: 0, page: 0xCD, offset: 0xB9, value: 0 } |
|
- { lane: 6, bank: 0, page: 0xCD, offset: 0xBB, value: 0 } |
|
- { lane: 7, bank: 0, page: 0xCD, offset: 0xBD, value: 0 } |
|
- { lane: 8, bank: 0, page: 0xCD, offset: 0xBF, value: 0 } |
|
|
|
- name: "tia_peak" |
|
description: "TIA:PEAK" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xCD, offset: 0xC1, value: 255 } |
|
- { lane: 2, bank: 0, page: 0xCD, offset: 0xC3, value: 255 } |
|
- { lane: 3, bank: 0, page: 0xCD, offset: 0xC5, value: 255 } |
|
- { lane: 4, bank: 0, page: 0xCD, offset: 0xC7, value: 255 } |
|
- { lane: 5, bank: 0, page: 0xCD, offset: 0xC9, value: 255 } |
|
- { lane: 6, bank: 0, page: 0xCD, offset: 0xCB, value: 255 } |
|
- { lane: 7, bank: 0, page: 0xCD, offset: 0xCD, value: 255 } |
|
- { lane: 8, bank: 0, page: 0xCD, offset: 0xCF, value: 255 } |
|
|
|
- name: "pol" |
|
description: "TIA:POL" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT0 |
|
- { lane: 2, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT1 |
|
- { lane: 3, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT2 |
|
- { lane: 4, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT3 |
|
- { lane: 5, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT4 |
|
- { lane: 6, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT5 |
|
- { lane: 7, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT6 |
|
- { lane: 8, bank: 0, page: 0xCC, offset: 0x95, value: 0 } # BIT7 |
|
|
|
- name: "rsscall_low" |
|
description: "TIA:RSSCALL" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT0 |
|
- { lane: 2, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT1 |
|
- { lane: 3, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT2 |
|
- { lane: 4, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT3 |
|
- { lane: 5, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT4 |
|
- { lane: 6, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT5 |
|
- { lane: 7, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT6 |
|
- { lane: 8, bank: 0, page: 0xCC, offset: 0x8F, value: 0 } # BIT7 |
|
|
|
|
|
- name: "rsscall_high" |
|
description: "TIA:RSSCALH" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT0 |
|
- { lane: 2, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT1 |
|
- { lane: 3, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT2 |
|
- { lane: 4, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT3 |
|
- { lane: 5, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT4 |
|
- { lane: 6, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT5 |
|
- { lane: 7, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT6 |
|
- { lane: 8, bank: 0, page: 0xCC, offset: 0x91, value: 0 } # BIT7 |
|
|
|
- name: "hpwr_op" |
|
description: "TIA:HPwrOp" |
|
registers: |
|
- { lane: 1, bank: 0, page: 0xCC, offset: 0x9F, value: 0 } # BIT4-BIT7 |
|
- { lane: 2, bank: 0, page: 0xCC, offset: 0x9F, value: 0 } # BIT0-BIT3 |
|
- { lane: 3, bank: 0, page: 0xCC, offset: 0xA1, value: 0 } # BIT4-BIT7 |
|
- { lane: 4, bank: 0, page: 0xCC, offset: 0xA1, value: 0 } # BIT0-BIT3 |
|
- { lane: 5, bank: 0, page: 0xCC, offset: 0xA3, value: 0 } # BIT4-BIT7 |
|
- { lane: 6, bank: 0, page: 0xCC, offset: 0xA3, value: 0 } # BIT0-BIT3 |
|
- { lane: 7, bank: 0, page: 0xCC, offset: 0xA5, value: 0 } # BIT4-BIT7 |
|
- { lane: 8, bank: 0, page: 0xCC, offset: 0xA5, value: 0 } # BIT0-BIT3 |
|
|
|
|
|
|
|
|