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OCS_TMP/note-1121

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RETIMER_LENGTH_MAP = {
# Retimer 1
(1, 0): (3585, 3585),
(1, 1): (3519, 3763),
(1, 2): (2476, 3578),
(1, 3): (3654, 3448),
(1, 4): (3677, 3317),
(1, 5): (3154, 3357),
(1, 6): (3437, 3800),
(1, 7): (3405, 4414),
(1, 8): (3918, 3528),
(1, 9): (3666, 3740),
(1, 10): (3717, 3681),
(1, 11): (4016, 3524),
(1, 12): (3645, 3610),
(1, 13): (4036, 3977),
(1, 14): (4919, 3508),
(1, 15): (4573, 3670),
# Retimer 2
(2, 0): (3978, 5829),
(2, 1): (4331, 5693),
(2, 2): (4088, 6285),
(2, 3): (4604, 5508),
(2, 4): (4319, 5720),
(2, 5): (4756, 5905),
(2, 6): (4347, 6915),
(2, 7): (5146, 6691),
(2, 8): (4658, 4942),
(2, 9): (4472, 5239),
(2, 10): (4479, 6250),
(2, 11): (4480, 5087),
(2, 12): (4515, 5243),
(2, 13): (4730, 4846),
(2, 14): (5346, 4835),
(2, 15): (5618, 5300),
# Retimer 3
(3, 0): (3524, 3516),
(3, 1): (4335, 3580),
(3, 2): (3723, 3547),
(3, 3): (3495, 3675),
(3, 4): (3802, 3125),
(3, 5): (3524, 2960),
(3, 6): (3647, 2416),
(3, 7): (3183, 3639),
(3, 8): (6371, 5361),
(3, 9): (6304, 4306),
(3, 10): (5160, 4167),
(3, 11): (5242, 4394),
(3, 12): (5237, 4191),
(3, 13): (5118, 4166),
(3, 14): (5156, 4242),
(3, 15): (5413, 4383),
# Retimer 4
(4, 0): (3788, 3424),
(4, 1): (4019, 3645),
(4, 2): (3589, 3235),
(4, 3): (3517, 3378),
(4, 4): (3502, 3514),
(4, 5): (3497, 3629),
(4, 6): (3585, 3824),
(4, 7): (3906, 3607),
(4, 8): (5395, 6109),
(4, 9): (6548, 5727),
(4, 10): (5378, 4535),
(4, 11): (5434, 4596),
(4, 12): (5427, 4546),
(4, 13): (5515, 4686),
(4, 14): (5419, 4646),
(4, 15): (5411, 5163),
}
Host Exp Slot Lane RTMR LossAlign DecodeErr RxValidNeg TsParity NonExist SkpParity Eye PCB-Length HighFreq LowFreq TiaPeak
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10.57.216.111 8 6 7 1,14 0 0 2 0 0 40 (-42.0,31.0);(-0.03,0.25) 3585,3508 140 0 255
10.57.216.111 8 6 0 2,6 0 0 2 0 0 3 (-67.0,72.0);(-0.06,0.28) 5156,6915 0 0 0
10.57.216.111 8 6 6 3,14 503 2 2 0 122 0 (-27.0,24.0);(-0.03,0.22) 4347,4242 0 0 255
10.57.216.111 8 0 1 4,0 178 1 2 1 42 0 (-67.0,65.0);(-0.09,0.22) 3918,3424 0 0 255
Host Exp Slot Lane RTMR LossAlign DecodeErr RxValidNeg TsParity NonExist SkpParity Eye PCB-Length HighFreq LowFreq TiaPeak
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10.57.216.112 8 6 4 1,6 0 0 2 0 0 1 (-58.0,72.0);(-0.06,0.25) 5419,3800 0 0 255
10.57.216.112 8 0 0 2,0 2614 13 0 0 255 16 (-27.0,56.0);(-0.06,0.22) 6371,5829 0 0 0 Err爆255，EQ不足
10.57.216.112 8 0 6 3,8 240 1 2 0 58 66 (-45.0,49.0);(-0.09,0.25) 3978,5361 0 0 255
Host Exp Slot Lane RTMR LossAlign DecodeErr RxValidNeg TsParity NonExist SkpParity Eye PCB-Length HighFreq LowFreq TiaPeak
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10.57.216.113 8 6 0 2,6 486 2 2 0 118 7 (-42.0,56.0);(-0.06,0.31) 5156,6915 0 0 0
10.57.216.113 8 2 1 4,2 0 0 2 0 0 1 (-38.0,33.0);(-0.03,0.25) 3717,3235 140 0 255
Host Exp Slot Lane RTMR LossAlign DecodeErr RxValidNeg TsParity NonExist SkpParity Eye PCB-Length HighFreq LowFreq TiaPeak
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10.57.216.114 8 6 4 1,6 990 4 2 0 240 3 (-18.0,6.0);(0.0,0.28) 5419,3800 70 0 255
10.57.216.114 8 6 7 1,14 236 1 2 0 57 12 (-38.0,56.0);(-0.03,0.22) 3585,3508 140 0 255
10.57.216.114 8 2 0 2,2 240 1 2 0 58 0 (-51.0,51.0);(-0.06,0.28) 5160,6285 0 0 0
10.57.216.114 8 6 0 2,6 646 3 2 0 156 255 (-51.0,58.0);(-0.09,0.25) 5156,6915 0 0 0 可能Err 255
Host Exp Slot Lane RTMR LossAlign DecodeErr RxValidNeg TsParity NonExist SkpParity Eye PCB-Length HighFreq LowFreq TiaPeak
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10.57.216.111 6 2 7 1,10 1648 6 2 79 255 0 (-81.0,92.0);(-0.09,0.31) 3717,3681 0 0 255
Host Exp Slot Lane RTMR LossAlign DecodeErr RxValidNeg TsParity NonExist SkpParity Eye PCB-Length HighFreq LowFreq TiaPeak
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10.57.216.112 6 3 0 2,3 0 0 2 0 0 1 (-65.0,31.0);(0.0,0.28) 4604,5508 140 0 255
Host Exp Slot Lane RTMR LossAlign DecodeErr RxValidNeg TsParity NonExist SkpParity Eye PCB-Length HighFreq LowFreq TiaPeak
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10.57.216.113 4 4 0 2,4 250 2 2 2 59 0 (-78.0,51.0);(-0.06,0.22) 4319,5720 0 0 255
10.57.216.113 4 6 1 4,6 264 1 2 0 64 0 (-31.0,29.0);(-0.03,0.28) 3585,3824 140 0 255
Host Exp Slot Lane RTMR LossAlign DecodeErr RxValidNeg TsParity NonExist SkpParity Eye PCB-Length HighFreq LowFreq TiaPeak
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10.57.216.112 4 2 0 2,2 783 3 2 0 190 27 (-33.0,24.0);(-0.06,0.31) 4088,6285 140 0 255
10.57.216.112 4 6 3 2,14 0 0 2 0 0 3 (-40.0,47.0);(-0.03,0.22) 5346,4835 0 0 255
Host Exp Slot Lane RTMR LossAlign DecodeErr RxValidNeg TsParity NonExist SkpParity Eye PCB-Length HighFreq LowFreq TiaPeak
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10.57.216.114 4 4 6 3,12 0 0 2 0 0 2 (-90.0,38.0);(-0.12,0.25) 5237,4191 0 0 255
Host Exp Slot Lane RTMR LossAlign DecodeErr RxValidNeg TsParity NonExist SkpParity Eye PCB-Length HighFreq LowFreq TiaPeak
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10.57.216.111 2 4 7 1,12 0 0 2 0 0 1 (-60.0,69.0);(-0.06,0.25) 5427,3610 0 128 112
10.57.216.111 2 4 3 2,12 854 4 2 0 206 36 (-38.0,74.0);(-0.06,0.28) 5237,5243 0 128 0
Host Exp Slot Lane RTMR LossAlign DecodeErr RxValidNeg TsParity NonExist SkpParity Eye PCB-Length HighFreq LowFreq TiaPeak
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10.57.216.112 2 5 3 2,13 0 0 2 0 0 3 (-40.0,54.0);(-0.06,0.28) 5118,4846 0 0 255
10.57.216.112 2 6 3 2,14 202 1 2 0 49 28 (-29.0,29.0);(-0.03,0.25) 5156,4835 0 0 255
10.57.216.112 2 7 3 2,15 0 0 2 0 0 20 (-27.0,49.0);(-0.06,0.28) 5413,5300 0 0 255
10.57.216.112 2 3 1 4,3 716 3 2 0 173 3 (-63.0,51.0);(-0.06,0.25) 3654,3378 140 0 255
Host Exp Slot Lane RTMR LossAlign DecodeErr RxValidNeg TsParity NonExist SkpParity Eye PCB-Length HighFreq LowFreq TiaPeak
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10.57.216.113 2 4 3 2,12 0 0 2 0 0 1 (-56.0,63.0);(-0.06,0.25) 5237,5243 0 0 255
Host Exp Slot Lane RTMR LossAlign DecodeErr RxValidNeg TsParity NonExist SkpParity Eye PCB-Length HighFreq LowFreq TiaPeak
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10.57.216.114 2 1 3 2,9 240 1 2 0 58 2 (-33.0,67.0);(-0.12,0.25) 6304,5239 0 0 128
10.57.216.114 2 2 3 2,10 0 0 2 0 0 2 (-60.0,51.0);(-0.09,0.28) 5160,6250 0 0 255
10.57.216.114 2 6 3 2,14 0 0 2 0 0 19 (-69.0,72.0);(-0.09,0.25) 5156,4835 0 0 1
10.57.216.114 2 6 2 4,14 0 0 2 0 0 55 (-78.0,38.0);(-0.06,0.31) 4919,4646 0 0 255
11.20：
Host Exp Rtmr Port Speed Width Recovery
------------------------------------------------------------------------------
10.57.216.111 6 1 0 Gen5 8 10
10.57.216.111 6 1 4 Gen5 8 226
10.57.216.111 6 2 0 Gen5 8 5
10.57.216.111 6 2 4 Gen5 8 5
10.57.216.111 6 3 0 Gen5 8 838
10.57.216.111 6 3 4 Gen5 8 5
10.57.216.111 6 4 0 Gen5 8 5
10.57.216.111 6 4 4 Gen5 8 5
10.57.216.112 6 1 0 Gen5 8 7
10.57.216.112 6 1 4 Gen5 8 42
10.57.216.112 6 2 0 Gen5 8 5
10.57.216.112 6 2 4 Gen5 8 6
10.57.216.112 6 3 0 Gen5 8 4889
10.57.216.112 6 3 4 Gen5 8 6
10.57.216.112 6 4 0 Gen5 8 5
10.57.216.112 6 4 4 Gen5 8 5
10.57.216.113 6 1 0 Gen5 8 7
10.57.216.113 6 1 4 Gen5 8 42
10.57.216.113 6 2 0 Gen5 8 5
10.57.216.113 6 2 4 Gen5 8 6
10.57.216.113 6 3 0 Gen5 8 4889
10.57.216.113 6 3 4 Gen5 8 6
10.57.216.113 6 4 0 Gen5 8 5
10.57.216.113 6 4 4 Gen5 8 5
10.57.216.114 6 1 0 Gen5 8 10
10.57.216.114 6 1 4 Gen5 8 226
10.57.216.114 6 2 0 Gen5 8 5
10.57.216.114 6 2 4 Gen5 8 5
10.57.216.114 6 3 0 Gen5 8 838
10.57.216.114 6 3 4 Gen5 8 5
10.57.216.114 6 4 0 Gen5 8 5
10.57.216.114 6 4 4 Gen5 8 5
Host Exp Slot Lane RTMR LossAlign DecodeErr RxValidNeg TsParity NonExist SkpParity Eye PCB-Length HighFreq LowFreq TiaPeak
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10.57.216.111 6 2 7 1,10 1103 4 2 69 255 0 (-65.0,60.0);(-0.06,0.28) 3717,3681 50 128 255
10.57.216.111 6 4 5 3,4 27404 103 2 0 255 7 (-6.0,4.0);(0.0,0.25) 3802,3125 50 128 255
10.57.216.112 6 6 5 3,6 1868 7 2 0 255 0 (-40.0,15.0);(-0.03,0.22) 3647,2416 50 128 255
10.57.216.113 6 6 4 1,6 276 1 2 0 67 0 (-2.0,0.0);(0.0,-0.03) 3437,3800 50 128 255
10.57.216.113 6 0 5 3,0 264 1 2 0 64 0 (-27.0,22.0);(-0.03,0.22) 3524,3516 50 128 255
10.57.216.113 6 4 5 3,4 65535 255 2 0 255 202 (-78.0,67.0);(-0.06,0.22) 3802,3125 50 128 255
10.57.216.113 6 6 5 3,6 264 1 2 0 64 0 (0.0,22.0);(0.0,0.25) 3647,2416 50 128 255
1119:
Host Exp Slot Lane RTMR LossAlign DecodeErr RxValidNeg TsParity NonExist SkpParity Eye PCB-Length HighFreq LowFreq TiaPeak
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10.57.216.111 4 7 4 1,7 0 0 2 0 0 52 (0.0,0.0);(0.0,-0.03) 3405,4414 0 128 112
10.57.216.113 4 1 1 4,1 0 0 2 0 0 9 (-56.0,51.0);(-0.06,0.28) 4019,3645 180 128 150
10.57.216.112 4 3 4 1,3 301 1 2 0 73 41 (-24.0,31.0);(0.0,0.25) 3654,3448 0 128 112
10.57.216.112 4 4 5 3,4 0 0 2 0 0 2 (0.0,0.0);(0.0,0.25) 3802,3125 0 128 112
10.57.216.114 4 7 3 2,15 0 0 2 0 0 2 (-42.0,76.0);(-0.03,0.25) 5618,5300 100 128 112
10.57.216.114 4 0 6 3,8 0 0 2 0 0 8 (-54.0,38.0);(-0.12,0.25) 6371,5361 200 128 112
10.57.216.114 4 6 1 4,6 0 0 2 0 0 11 (-42.0,29.0);(-0.06,0.16) 3585,3824 100 128 112
Host Exp Slot Lane RTMR LossAlign DecodeErr RxValidNeg TsParity NonExist SkpParity Eye PCB-Length HighFreq LowFreq TiaPeak
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10.57.216.112 6 3 0 2,3 0 0 2 0 0 1 (-67.0,13.0);(-0.03,0.25) 4604,5508 255 120 255
10.57.216.113 6 6 3 2,14 272 1 2 0 66 0 (-11.0,11.0);(0.0,0.25) 5346,4835 255 120 255
10.57.216.113 6 0 5 3,0 268 1 2 0 65 0 (-22.0,24.0);(-0.03,0.22) 3524,3516 255 120 255
10.57.216.113 6 3 2 4,11 0 0 2 0 0 1 (-54.0,54.0);(-0.09,0.25) 5434,4596 255 120 255
10.57.216.114 6 4 7 1,12 0 0 2 0 0 1 (-40.0,67.0);(-0.06,0.25) 3645,3610 255 120 255
10.57.216.114 6 7 6 3,15 528 2 2 0 128 2 (-81.0,56.0);(-0.12,0.28) 5413,4383 255 120 255
11-18:
Host Exp Slot Lane RTMR LossAlign DecodeErr RxValidNeg TsParity NonExist SkpParity Eye PCB-Length HighFreq LowFreq TiaPeak
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10.57.216.111 6 2 7 1,10 5496 20 3 210 255 0 (-65.0,69.0);(-0.06,0.31) 3717,3681 150 128 112
10.57.216.111 6 4 3 2,12 1642 6 2 0 255 17 (-54.0,18.0);(0.0,0.25) 4515,5243 100 128 0 未调
10.57.216.111 6 0 5 3,0 0 0 2 0 0 1 (-31.0,27.0);(-0.03,0.25) 3524,3516 150 128 112
10.57.216.111 6 0 6 3,8 0 0 2 0 0 1 (-45.0,36.0);(-0.03,0.22) 6371,5361 0 128 0
10.57.216.114 6 4 2 4,12 0 0 2 0 0 10 (-36.0,72.0);(-0.06,0.34) 5427,4546 50 50 112
10.57.216.113 6 7 3 2,15 18564 68 2 0 255 0 (-2.0,38.0);(0.0,0.19) 5618,5300 100 128 0 255,128,200
10.57.216.111 4 7 3 2,15 0 0 2 0 0 1 (-27.0,45.0);(-0.03,0.25) 5618,5300 100 128 0
10.57.216.111 4 4 5 3,4 0 0 2 0 0 2 (-90.0,36.0);(-0.09,0.25) 3802,3125 180 128 200
10.57.216.111 4 7 2 4,15 0 0 2 0 0 1 (-40.0,54.0);(-0.06,0.25) 5411,5163 100 128 0
10.57.216.113 4 1 5 3,1 0 0 2 2 0 0 (-67.0,56.0);(-0.03,0.22) 4335,3580 100 128 112
10.57.216.112 4 4 7 1,12 0 0 2 0 0 4 (-54.0,69.0);(-0.12,0.25) 3645,3610 180 128 112
10.57.216.112 4 6 3 2,14 1417 5 2 0 255 213 (-54.0,56.0);(-0.03,0.19) 5346,4835 100 128 112 150,128,112
10.57.216.112 4 1 5 3,1 0 0 2 0 0 4 (-6.0,20.0);(0.0,-0.03) 4335,3580 100 128 112 200,200,112
10.57.216.112 4 0 6 3,8 0 0 2 0 0 1 (-40.0,40.0);(0.0,0.22) 6371,5361 200 50 0
10.57.216.112 4 1 1 4,1 11199 41 2 0 255 255 (-20.0,11.0);(0.0,0.22) 4019,3645 100 128 112 200,200,112
10.57.216.114 4 6 3 2,14 0 0 2 0 0 6 (-65.0,56.0);(-0.03,0.22) 5346,4835 100 128 112
10.57.216.114 4 7 3 2,15 0 0 2 0 0 5 (-38.0,49.0);(-0.03,0.22) 5618,5300 100 128 0
10.57.216.114 4 3 6 3,11 0 0 2 0 0 2 (-78.0,36.0);(-0.06,0.25) 5242,4394 100 128 112
Host Exp Slot Lane RTMR LossAlign DecodeErr RxValidNeg TsParity NonExist SkpParity Eye PCB-Length HighFreq LowFreq TiaPeak
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10.57.216.100 6 2 3 2,10 0 0 2 0 0 6 (-2.0,2.0);(0.0,0.22) 4479,6250 100 128 0
10.57.216.100 6 3 3 2,11 0 0 2 0 0 11 (-9.0,22.0);(0.0,0.19) 4480,5087 100 128 0
10.57.216.100 6 2 5 3,2 268 1 2 1 65 12 (-29.0,22.0);(0.0,0.25) 3723,3547 180 128 112
10.57.216.100 6 2 6 3,10 0 0 4 1 0 7 (-2.0,47.0);(0.0,-0.03) 5160,4167 100 128 112
10.57.216.101 6 3 4 1,3 0 0 2 2 0 0 (-42.0,51.0);(0.0,0.25) 3654,3448 180 128 200
10.57.216.101 6 6 4 1,6 272 1 2 0 66 0 (-58.0,47.0);(-0.06,0.22) 3437,3800 180 128 112
10.57.216.101 6 4 7 1,12 121 1 2 9 29 2 (-45.0,31.0);(-0.03,0.25) 3645,3610 180 128 112
10.57.216.101 6 3 0 2,3 2 0 3 0 0 0 (-31.0,38.0);(-0.03,0.22) 4604,5508 100 128 0
10.57.216.101 6 6 0 2,6 0 0 4 0 0 1 (-24.0,33.0);(-0.03,0.25) 4347,6915 0 128 0
10.57.216.101 6 3 3 2,11 273 1 2 3 66 3 (0.0,6.0);(0.0,0.22) 4480,5087 100 128 0
10.57.216.101 6 4 3 2,12 56 1 2 0 13 0 (-49.0,45.0);(-0.06,0.12) 4515,5243 100 128 0
10.57.216.101 6 6 3 2,14 0 0 2 0 0 1 (-47.0,60.0);(-0.06,0.19) 5346,4835 100 128 112
10.57.216.101 6 3 6 3,11 3469 14 4 1 255 82 (-27.0,0.0);(0.0,0.12) 5242,4394 100 128 112
10.57.216.101 6 3 1 4,3 268 3 2 255 66 0 (-40.0,40.0);(-0.03,0.22) 3517,3378 180 128 200
10.57.216.101 6 3 2 4,11 532 2 2 0 129 5 (-47.0,42.0);(-0.06,0.25) 5434,4596 100 128 112
10.57.216.101 6 6 2 4,14 1064 4 2 0 255 5 (-54.0,47.0);(-0.09,0.22) 5419,4646 100 128 112
11.14：
112p4 rtmr 2,14 3
111p6 rtmr 2,12 272
114p6 rtmr 4,12 63
114p6 rtmr 1,12 2
113p6 rtmr 2,15 4092 5618-5300 old:67,78 new: 100,tia:112
第一次建链
Host Exp Slot Lane RT_ID RT_Lane Loss Align Decode Err TS Parity Non Exist Sym Skip Parity
------------------------------------------------------------------------------------------------------------------------
10.57.216.112 4 6 3 2 14 4957 18 0 255 4 (5346, 4835), 32,93 改为 100,112
10.57.216.113 6 4 5 3 4 532 2 0 129 1 (3802, 3125) old:180,150 new:109,200 眼偏大，重新校准mgc后观察
第二次建链：
10.57.216.111 4 4 3 2 12 276 1 0 67 0 (4515, 5243) old: 130,150 new:74,60
10.57.216.111 6 2 7 1 10 276 1 15 67 0 (3717, 3681) old: 50,112 new:114,185
10.57.216.111 6 0 6 3 8 0 0 0 0 1 (6371, 5361) old: 0,0 new: 0,51
第三次建链：
10.57.216.112 4 1 5 3 1 0 0 4 1 0 (3524, 3516) old:50,150 new:83,150 改后：150,150
10.57.216.111 6 2 7 1 10 276 1 14 67 0
10.57.216.111 6 0 6 3 8 0 0 0 0 1